Generally, a multi-state indicator is used to represent a voltage of a voltage input end in the digital format. Please refer to FIG. 1(a) and FIG. 1(b). FIG. 1(a) and FIG. 1(b) are schematic diagrams of operational segments and circuits of a three-state indicator 100 according to the prior art. When the three-stage indicator 100 is applied to a circuit having a voltage distributed from Vss to Vdd (Vdd>Vss), the three-stage indicator 100 determines that an input voltage Vin is Vdd, VM, or Vss, and puts the input voltage Vin into a two-bit indication signal (Vout2, Vout1), i.e., the indication signal (Vout2, Vout1) is represented in the digital indication signal output “1/0” format, so as to be provided to subsequent circuits.
Please refer to FIG. 1(a), a voltage segment from Vdd to Vss is divided into two voltage segments—a first voltage segment I formed between VM and Vss and a second voltage segment II formed between Vdd and VM. A first reference voltage Vref1 is selected from the first voltage segment I, and a second reference voltage Vref2 is selected from the second voltage segment II. As shown in FIG. 1(b), the first reference voltage Vref1 and the second reference voltage Vref2 are generated by a reference voltage generator 101, and the voltages Vdd, Vref2, Vref1, and Vss are provided to the three-state detector 103. The above voltages are compared with the input voltage Vin in the three-state detector 103, and the input voltage Vin is determined to be one of the voltages according to the indication signal (Vout2, Vout1).
FIG. 2(a) is a schematic diagram of a differential comparator 2. When an input voltage Vin2 at a positive input end of the differential comparator 2 is larger than an input voltage Vin1 at a negative input end, a digital indication signal “1” is generated at an output end Vout of the differential comparator 2. On the contrary, when the input voltage Vin2 at the positive input end of the differential comparator 2 is smaller than the input voltage Vin1 at the negative input end, a digital indication signal “0” is generated at the output end Vout of the differential comparator 2.
Please refer to FIG. 2(b). FIG. 2(b) is a schematic diagram of a three-state indicator implemented with two differential comparators in the prior art. The three-state detector 103 of the three-state indicator 100 is composed of a first differential comparator 21 and a second differential comparator 22. The first differential comparator 21 has a positive input end for receiving an input voltage Vin, a negative input end for receiving a first reference voltage Vref1, and an output end for generating the first bit Vout1 of the indication signal (Vout2, Vout1). The second differential comparator 22 has a positive input end for receiving the input voltage Vin, a negative input end for receiving a second reference voltage Vref2, and an output end for generating the second bit Vout2 of the indication signal (Vout2, Vout1).
It can be seen that when the input voltage Vin is at the first level Vss, the indication signal (Vout2, Vout1) is (0, 0); when the input voltage Vin is at the second level VM, the indication signal (Vout2, Vout1) is (0, 1); when the input voltage Vin is at the third level Vdd, the indication signal (Vout2, Vout1) is (1, 1). As shown in FIG. 2(b), since power of the first differential comparator 21 and the second differential comparator 22 is supplied by Vdd and Vss, the logic “1” of the first differential comparator 21 and the second differential comparator 22 is Vdd, while the logic “0” is Vss.
The approach of implementing the three-state indicator 100 with the differential comparator 2 in the prior art can also be applied to other multi-state indicators. Please refer to FIG. 2(c) and FIG. 2(d) at the same time. FIG. 2(c) and FIG. 2(d) are schematic diagrams of operation segments and circuits of a four-state indicator 200.
As shown in FIG. 2(c), voltage differences of four voltages Vss, VML, VMH, and Vdd (where Vss<VML<VMH<Vdd), used for comparison by the four-state indicator 200, are divided into three voltage segments I, II, and III. The first reference voltage Vref1 is selected from the first voltage segment I, the second reference voltage Vref2 is selected from the second voltage segment II, and the third reference voltage Vref3 is selected from the third voltage segment III. As shown in FIG. 2(d), in addition to the three reference voltages Vref1, Vref2, and Vref3 outputted by the reference voltage generator 201, Vdd and Vss, are supplied to the voltage input end of the four-state detector 203, which comprises three differential comparator circuits 23, 24, and 25. Besides taking Vin as input voltages of positive input ends, the differential comparator circuits 23, 24, and 25 respectively take reference voltages Vref1, Vref2, and Vref3 as input voltages of negative input ends, and comparison results of the differential comparator circuits 23, 24, and 25 are taken as an indication signal (Vout3, Vout2, Vout1) generated by the four-state indicator 200. Since power of the differential comparator circuits 23, 24, and 25 is supplied by Vdd and Vss, the logic “1” outputted by the differential comparator circuits 23, 24, and 25 is Vdd, while the logic “0” outputted by differential comparator circuits 23, 24, and 25 is Vss.
However, circuit design of the conventional differential comparator is rather complex. Once the number of to-be-identified states increase, accordingly, the circuit design complexity increases greatly, resulting in difficulties in the circuit design. An area of the differential comparator is excessively large, causing a significant increment in production cost. In addition, the circuit design of the differential comparator has a static current problem, causing additional power consumption.